It seems like we should be able to build this processor and board set for real. And how cool would it be if we did?

I'm not an engineer, but 16 instructions, a primary register and backup register, registers are 16 bit (technically 14bit), input and output flow... Not only that the chip would probably have very few transistors and run low power. Naturally you can't put a full blown OS on it, but for fun people make 4-8 bit computers just because they can, and manually creating a breadboard to simulate this 4bit processor seems like it could be done quite easily, or if there's enough engineers who want to play with a simple parallel CPU they could make thousands of these and sell them to enthusiasts.

Let's see. Probably internal memory for ROM would be 20-24 bits, or 40-48 bytes of rom programming per chip.

So if we try to map the chip with pins, it would probably be

1 power
1 ground/out
4 io pins (each direction)
4 timing/ready pins (each direction)
1 external stepper pin? (to single step?)
1 ??? (use stepper? or possibly full output of PC, Acc, Bak, and instruction on each step?)

so 10-12 pins total.

Base BIOS would probably be by default to do a binary left, top, right, programming mode (never program down). This means that both the IO and the timing pins would be used during power on (and simplify programming the chips in parallel from one chip rather than each chip individually). By default the chip would read from any of the inputs and once it's filled it would then take over and either return a 'done' signal to the previous chip, or it would forward instructions to the next chip in the sequence. Once the chip has been programmed and not waiting on anything it would start executing, likely being blocked until all the nearby chips are programmed.

Thoughts? Any engineers with something to add or suggest? Seeing as the 6502 had about 4000 transistors for the whole chip, you're probably looking at closer to 400 for the TIS-100, the most complex being the add/subtract (and subtract using 2's compliment means only the add is really used).

I wonder alternatively if a 5bit address bus (32 instruction ROM, or 80-96 bytes) would be attempted instead while needing no more complexity on the creation of the chip, and would work just as well or better, since i know programming some of the more complex problems usually just required breaking the logic into multiple parts and most of it was waiting for the logic to transpire than for the actual parallel nature to be taken advantage of.

Heh... now i want to see a TIS-200 where they do just that, double the programmable ROM and make a scrolling window so you could access twice or more of the ROM space while leaving the UI the same, except watching it in fast execution wouldn't look as glamorous unless zoomed out or something...

Hmmm although maybe not the best place to put this, i need to dump my thoughts somewhere.

I've been going over a minimal instruction set required, and i think i have it (well there's some redundancy but for the sake of flexibility)

AND Reg, Reg
AND Reg, Imm
OR Reg, Reg
OR Reg, Imm
XOR Reg, Reg
XOR Reg, Imm

MOV Reg, [Imm]
MOV Reg, [Reg]
MOV [Imm], Reg
MOV [Reg], Reg

ADC Reg, Reg
ADD Reg, Imm
ADDC Reg, Imm
ADDZ Reg, Imm
ADDL Reg, Imm

ROL Reg, Imm8 (left shift, rotating)

Registers would include Accumulator, X, Y, and PC. Either 8 or 16bits

And that's it.

Although there's no comparing, jump, or direct handling of the carry flag, you could do a couple instructions to get a similar result. There's also no setting a register directly; So let's cover those.

The carry flag:

Removing the carry flag is simple, ADC against 0 and the carry goes away. to set it, ADC against the largest number (or highest bit) with the register against itself, and you set the flag. The only assumption is you have a register free to work with, which will probably be the accumulator.

clear carry
XOR ACC, ACC
ADC ACC, ACC

set carry
OR ACC, -1
ADC ACC, ACC

Next, jumping and logic. Notice the ADDC and ADDZ, those are ADD if carry and ADD if Zero. Since the program counter is an accessible public register, you simply add/subtract to the PC and you will jump. The Zero flag is always adjusted based on the contents of the Accumulator register, so that is where your logic will likely often be at.

JMP 10 = ADD PC, 10

Next, setting a register. Since there's no MOV Reg, Imm, that means you can't just set a register with a full fixed value. But you can using 2 steps. First clearing the register, and next ORing them on, or doing a non-carry addition.

Set 10
XOR ACC, ACC
OR ACC, 10
(Note, not to be used with PC, as the XOR would reset it's starting location to 0, unless instruction 0 was ADC PC, reg which would let you set it based on another register)

Next. There's no subtraction. This is true, but using 2's compliment you can get the same result, although maybe being able to add 1 without affecting the carry would make it easier, although having a jump/carry to keep in mind if the carry exists before starting works too. So SUB ACC, X is equal to:

XOR X, -1
ADD X, 1
ADC ACC, X

There is only the left shift. However since it's a rotating shift you can go quite a bit over to effectively give it a right shift. After shifting you'd probably AND to keep the bits you really wanted on, in case there's overflow and not giving you odd multiplication results.

Although there's no ADDNC or ADDNZ you can do a true jump following another jump to get around that.

ADDC PC, IfCarry
ADD PC, NotCarryDestination
IfCarry:

A note, originally ADD reg, Imm wasn't considered, and there was ADCC and ADCZ instead of ADDC and ADDZ, but the carry flag involved would have made it a headache to deal with (probably). Plus ADD reg, Imm makes it much easier to apply 2's compliment without worrying about the carry flag, or dealing with odd jump cases. It's apparent by stringing a few instructions together you can simulate larger or more complex instructions, so implementing a small set (plus the combinations for the register or having the decoder handle that) would probably do quite well. Also ADDC and ADDZ were considered to add two registers but as they are likely used for jumping or adjusting, making them immediate values seems more useful.

edit: Another note. I forgot to add this, but there's the ADDL or Add if less than 0. Not quite the same as Z or NZ, because it considers the highest bit and treats it as signed. So doing a compare against zero, and then doing the less-than you can get similar jump styles from JG, JGE, JL, JLE, JZ, JNZ, JC, JNC used in the x86 instruction set. Although upon reflection doing an AND of the highest bit and testing if it is zero would give you the same effect...

Registers X&Y are mostly more useful for source/destination registers for memory copying and the like (based on 6502) but nothing stopping one of them from a backup, immediate values, or a stack register.

Depending on the register's base size you'll limit yourself to 256bytes of memory or 64k of memory, since implementing 2 different memory size types would push it past 16 instructions. Still, 256 bytes at 2 bytes per instruction (when immediates at 8bits long), you can implement prime number testers, or a Fibonacci program easily enough.

So there's the dump of what I've been thinking the last couple days...

Sorry to bring this up, but did you do anything with this. It would be cool to build a hardware implementation of TIS.

OK there is a project if I have plenty, plenty, plenty of time...

Or you could implement it with FPGAs

Been thinking about this again, though come to a slightly different conclusion.

First apparently you can do everything you need with subleq, it does math/deltas, it does comparison and jumping. Subtract twice and you can add, adding something to itself and it's equal to shifting left once, etc

So, if you in theory did memory only (no registers, other than IP) then subleq mem,mem,destination will suffice.

However if you use registers, unless it's a mixed memory/register model like x86 does you'd need store/load along with subleq.

So: Minimum set
subleq
load
store

now if we break apart subleq you get the following: (2's compliment will make it subtract, or you invert the number to add)
xor
branch (brle, or jlez, or similar)
add

So now we have 5 instructions. Those are all you need. Not to say you want only that, but everything else can be built up and emulated.

Finally If we add shift right (shift left can be done by add), along with and & or, you get this final set of 8 (and some variations for immediate values)
load R,[mem]
store [mem],R
xor R,R
and R,R
or R,R
add R,R
shr R,R
branch R, DST (comparison type may extend beyond 1 instruction, maybe 4-6)

If you have a lot of registers, instead of R,R you have S,R,R where S is the stored register and R,R are the registers working. But otherwise very little changes above.

(technically you can do add with and/xor/lshift, but the number of cycles for carries may just be annoying)

Any instructions that would be very complex and slow would be candidates as separate instructions implemented at the hardware level. Like mul, div, floating point.